1. Field of the Invention
The present invention relates to a fabricating method of a semiconductor device. More particularly, the present invention relates to a fabricating method of an non-volatile memory.
2. Description of the Related Art
Memory is a semiconductor device designed to store data or parameters. With the production of increasingly powerful microprocessors, the size of the software programs that are operated by memory increases correspondingly. As a result, the demand for a high storage capacity memory is getting higher and higher. The challenge of producing memory with a larger storage capacitor in accordance with this trend is now the force driving the techniques and processes for developing highly integrated semiconductor devices.
Among the memory products, non-volatile memory is one type of memory device having the capacity for writing data into, reading data from and erasing stored data multiples of times. Moreover, data will be retained even if the power to the device is cut off. With these advantages, it has become one of the most widely adopted memory devices in personal computer and electronic equipment.
FIG. 1 is a schematic cross-sectional view of a trench-type device. As shown in FIG. 1, the substrate 100 has a plurality of trenches 102 with a trench device disposed in each trench 102. The trench device is a trench-type memory, for example, comprising a floating gate 104, a control gate 108 and a dielectric layer 106. The floating gate 104 and the control gate 108 are both fabricated from doped polysilicon material. Furthermore, there are source/drain regions 110 underneath the trench device. The source/drain regions 110 are formed by performing an ion implant process, for example.
However, with the increase in the level of integration, the distance separating two adjacent trench-type devices has to be reduced. In other words, the distance between the source/drain regions 110 has to be reduced. Because of the short distance separating the source/drain regions 110, some of the dopants in the source/drain regions 110 may diffuse into the substrate 100 leading to abnormal electrical punch through between adjacent source/drain regions 110. On the other hand, in the process of forming the control gate 108 using a doped polysilicon material, some of the dopants inside the control gate 108 will also diffuse into the source/drain regions 110 and expand the source/drain regions 110. This phenomenon further exacerbates the ease of forming an abnormal electrical punch through between neighboring source/drain regions 110. In some cases, some of the dopants may diffuse into the surrounding dielectric layer and seriously affect the ultimate reliability of the device. Furthermore, the control gate 108 formed from the doped polysilicon material has a higher line resistance. Hence, the performance of the device will also be affected.